Integrated circuit design includes selection and layout of gates also known as cells. The interconnections between the multiplicity of gates in an integrated circuit form signal paths. In most cases, the interconnections between gates form an interconnect tree (as shown in FIG. 1). The resistive, capacitive and inductive attributes of interconnect lines form gate loads at the respective gate outputs and contribute to signal time delays.
With interconnect delays dominating overall path delays for deep-submicron integrated circuits, heuristics for logic synthesis and layout optimization need to accurately model interconnect effects. Accurate estimations of gate delay and slew time are required for a number of signal integrity and reliability checks. In synthesis and floorplanning, pre-layout gate delay estimation capability is needed. In post-layout timing analysis, existing accurate gate delay estimates are not efficient enough to be used in the typical incremental synthesis, layout or in-place optimization loop or during performance-driven area routing. In either context, accurate estimations of gate delay and slew time at the gate output, depend closely on an accurate model for the admittance of an interconnect tree load at the gate output. The present invention addresses these and related issues.